Senior Synthesis Engineer
Senior Synthesis Engineer
leadsoc technologies pvt ltd3-6 Years
- Posted 8 hours ago
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Job Description
About This Job
LeadSoc Technologies Pvt Ltd
Location: Bengaluru, Karnataka, India
Work Mode: On-site
Industry: Semiconductor Manufacturing
Job Description
Senior Synthesis Engineer
Experience Level :- 3yrs to 6yrs
Notice Period :- Immediate to 45 Days
Work Location :- Bangalore
Job Description – Senior Synthesis Engineer (VLSI)
Worked on 7nm/5nm/Future sub-micron Technologies.Hands on experience in Physical Synthesis with Multi corner & Multi-mode, Low Power, Performance and Area Goal using Fusion Compiler or Genus.Hands on experience in Logic equivalence check and low power check debugging and clean up using Conformal LEC or Formality.Familiar with pre-STA timing analysis using Primetime or Tempus.Familiar with low power check using Conformal Low Power or VCLP tool.Experience in verifying constraints quality and completeness.Understanding of UPF & Low power concepts.Familiar with functional ECO flow and implementation.Familiar with DFT Insertion and debugging basic DFT issues.Co-work with RTL, DFT and PD engineers to meet PPA targets.Well versed with TCL/Perl/Shell script.Self-starter and highly motivated.Strong debugging, initiative and analysis/problem solving skills.Minimum 3+ years of experience in Synthesis and Physical Synthesis
Mode of Work :- WFO
Employment Type :- Permanent
LeadSoc Technologies Pvt Ltd
Location: Bengaluru, Karnataka, India
Work Mode: On-site
Industry: Semiconductor Manufacturing
Job Description
Senior Synthesis Engineer
Experience Level :- 3yrs to 6yrs
Notice Period :- Immediate to 45 Days
Work Location :- Bangalore
Job Description – Senior Synthesis Engineer (VLSI)
Worked on 7nm/5nm/Future sub-micron Technologies.Hands on experience in Physical Synthesis with Multi corner & Multi-mode, Low Power, Performance and Area Goal using Fusion Compiler or Genus.Hands on experience in Logic equivalence check and low power check debugging and clean up using Conformal LEC or Formality.Familiar with pre-STA timing analysis using Primetime or Tempus.Familiar with low power check using Conformal Low Power or VCLP tool.Experience in verifying constraints quality and completeness.Understanding of UPF & Low power concepts.Familiar with functional ECO flow and implementation.Familiar with DFT Insertion and debugging basic DFT issues.Co-work with RTL, DFT and PD engineers to meet PPA targets.Well versed with TCL/Perl/Shell script.Self-starter and highly motivated.Strong debugging, initiative and analysis/problem solving skills.Minimum 3+ years of experience in Synthesis and Physical Synthesis
Mode of Work :- WFO
Employment Type :- Permanent
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Key Skills
Pre-STA timing analysis
DFT Insertion
Fusion Compiler
Conformal Low Power
Formality
Tempus
VCLP tool
Functional ECO flow
Logic equivalence check
UPF Low power concepts
Genus
Low power check
About Company
Skills:
Static Timing Analysis, Python, Tcl, SDC constraint authoring and management, primetime, Fusion Compiler, Physical-Aware Synthesis