boundary scan , logic bist , Test Automation, DFT Methodologies, Scan Design, Fault Simulation, ATE Programming, Design Debugging, DFT Architecture, Timing Analysis

Scan, HDLs, MBIST, DFT architecture definition, Tempus, ATPG flow implementation, scripting skills in Perl, Genus, tessent DFT, JTAG boundary scan, Cadence digital implementation tools

Pre-silicon DFT verification, Post-silicon validation, Yield improvement, BSCAN, Hierarchical multi-core test strategies, MBIST, Scripting and automation, Scan compression, GLS, Power-aware DFT, ATPG simulation, ATPG, Debug, DFT timing closure, LBIST, ATE test program development, Coverage closure, IJTAG, Silicon bring-up

SoC-level DFT Integration, JTAG IEEE 1149.1, DFT DRC and Debug, MBIST Implementation and Verification, ATPG and Fault Coverage Analysis, Scan Insertion and Scan Compression

occ, Memory-BIST, DFT architecture scan Insertion compression at core level and SoC level, SSN architecture, timing and no-timing simulations, clock architecture, ATPG pattern generation coverage analysis

Vcs, Perl, Python, Tcl, ATPG Fault Models, DFT Debugging, Siemens Tessent, Synopsys TestMAX, End-to-end DFT implementation, RTL SoC Design Flow, Cadence Modus, STA Timing Closure, MBIST LBIST, DFT Sign-off Fault Coverage, JTAG Boundary Scan – IEEE 1149.1, Scan Insertion Compression

logic bist , DFT architecture, Functional BIST, Digital design flows, Scan compression, SoC MCU architecture, DFT protocols