Noc, Usb, Vcs, DDR, Shell, Perl, Pcie, Ethernet, Python, Verdi, IUS, UVM environments, SystemVerilog UVM, GLS, coverage closure, debug tools, testbench architecture, Axi, IP SOC verification, Questa, CXL, CPU-based verification

System Verilog, HBM4, Assertion-based verification, Cadence Xcelium, Power-aware verification, silicon debug, Gate-level simulation, Uvm, Synopsys VCS, Asic Design Verification, Synopsys JasperGold, Verification management tools, VC Formal, LPDDR6, DRAM Memory Controller

Usb, C, C++, Debugging, Test Plan, Object Oriented Programming, Writing Test Cases, Oop, DDR, Ethernet, Pcie, Perl, Tcl, Function coverage, Coverage driven verification, Uvm, IP Subsystem SOC ASIC Verification, Axi, Code coverage analysis, CXL, Test bench development, Simulation, System-Verilog

C DPI Development, Hardware-Software Integration, Debugging Expertise, Scripting and Automation, Verification Planning, Uvm, systemverilog, SoC Verification, Coverage-Driven Verification

System Verilog, Assertion-based verification, Verification methodologies, Power-aware verification, Verification management tools, silicon debug, Gate-level simulation, Uvm, formal verification

Verilog, pre-silicon verification, EDA Tools, Uvm, systemverilog

Verilog, System Verilog, Synopsys VCS, Cadence IES, formal property checking tools, Uvm

Vcs, System Verilog, Verdi, DVE, Xcelium, Questa, Uvm, SVA assertions

Unix, Shell, Pcie, Linux, System Verilog, VIP coding, Coverage strategies and measurement, Constraint based Random verification, Skill, Test cases coding, Uvm, Digital Design and Verification methodologies, Python Script, DDR verification, Test Plan design