Design Verification Engineer
- Posted 2 months ago
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Job Description
Position: ASIC Design Verification Engineer
Location: Hyderabad
Experience: 3–5 Years
Hiring Design Verification Engineer with strong IP-level / Functional Verification experience using UVM to support high-quality IP development programs. If you enjoy solving real-world verification problems and contributing to high-quality IP delivery, this role offers an excellent opportunity to grow and make an impact.
Job Description:
- Hands-on experience in IP-level functional verification using SystemVerilog and UVM, including testbench development and test case creation.
- Perform RTL verification, debug functional issues, analyze waveforms/logs, and ensure quality IP delivery within project timelines.
- Solid understanding of digital design fundamentals and industry-standard verification methodologies.
- Exposure to on-chip bus and interface protocols such as AXI, AHB, and Ethernet for IP verification.
- Utilize scripting languages (Python, Perl, Shell) to support verification automation, regression, and productivity improvements.
Thanks,
Karthik Kumar
[Confidential Information]
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About Company
Skills:
Noc, Usb, Vcs, DDR, Shell, Perl, Pcie, Ethernet, Python, Verdi, IUS, UVM environments, SystemVerilog UVM, GLS, coverage closure, debug tools, testbench architecture, Axi, IP SOC verification, Questa, CXL, CPU-based verification
Skills:
C, Debugging, Verilog RTL, Verification Techniques, Communication Interfaces, Scripting and Automation, EDA Tools, Uvm, Digital and SoC Verification, C DPI, systemverilog
Skills:
System Verilog, Assertion-based verification, Cadence Xcelium, Power-aware verification, silicon debug, Gate-level simulation, Uvm, Synopsys VCS, Asic Design Verification, Synopsys JasperGold, Verification management tools, VC Formal
Skills:
Usb, C, C++, Debugging, Test Plan, Object Oriented Programming, Writing Test Cases, Oop, DDR, Ethernet, Pcie, Perl, Tcl, Function coverage, Coverage driven verification, Uvm, IP Subsystem SOC ASIC Verification, Axi, Code coverage analysis, CXL, Test bench development, Simulation, System-Verilog
Skills:
Unix, Shell, Pcie, Linux, System Verilog, VIP coding, Coverage strategies and measurement, Constraint based Random verification, Skill, Test cases coding, Uvm, Digital Design and Verification methodologies, Python Script, DDR verification, Test Plan design