Sed, Jtag, Awk, Tcl, debug skills, MBIST, gate-level simulation, Spyglass-DFT, test cost reduction analysis, Dft, ATPG, scan-stitching, Scan, scripting skills, LBIST, Tessent flow

test program development , boundary scan , Version Control Systems, Jtag, Memory BIST, TAP, Data Analysis Tools, Low Coverage Debug, Verification, Pattern Generation, Scan Synthesis, Implementation, Ate, Scan Architecture, ATPG, EDA Tools, Simulation, DFT Architecture

Jtag, DFT Engineer, DFT Manager, iJTAG, BSCAN, ATPG, technical ownership, DFT tools

boundary scan , logic bist , Test Automation, DFT Methodologies, Scan Design, Fault Simulation, ATE Programming, Design Debugging, DFT Architecture, Timing Analysis

Sed, Jtag, Awk, Tcl, debug skills, MBIST, gate-level simulation, Spyglass-DFT, test cost reduction analysis, Dft, ATPG, scan-stitching, Scan, scripting skills, LBIST, Tessent flow, post silicon support

memory test , Scripting Languages, Static Timing Analysis, Digital Logic Design, Jtag, Hdl, BIST Architecture, Simulation, IEEE1149.1, ASIC Logic Design Flow, Gates Verification, Scan ATPG, IEEE1500, Compression Techniques, Eco

boundary scan , ATPG (Automatic Test Pattern Generation), LBIST (Logic Built-In Self-Test), DFT DRC (Design Rule Checking), Jtag, Perl, Python, Tcl, LINT, ASIC design flow, cdc, Scan compression, Scan stitching, Low power DFT Techniques, RTL Coding, ATPG Coverage improvement, DFT STA Constraint development, Analog Phy DFT

SSN, MBIST, LBIST, Scan Insertion, IEEE1149.1 JTAG, IJTAG

Python Scripting, VecGen pattern generation, Synopsys VCS, SoC DFT integration, Synopsys MBIST SMS5, MBIST insertion, Top-level MBIST verification, MBIST repair schemes and memory test algorithms, MBIST diagnostics, Silicon bring-up and post-silicon debug, With-delay simulation and debug

Sed, Jtag, Awk, Tcl, DFT features, debug skills, MBIST, gate-level simulation, Spyglass-DFT, test cost reduction analysis, ATPG, scan-stitching, Scan, scripting skills, LBIST, Tessent flow, post silicon support