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Staff Engineer- DFT
Job Description
Responsibilities
- Manage hierarchical scan insertion and ATPG flow
- Integrate and verify MBIST at the RTL level
- Handle RTL integration, verification, gate-level coverage, and GLS enablement for LBIST
- Implement and verify IEEE1149.1 JTAG and IJTAG standards
- Lead post-silicon debug activities related to DFT patterns
- Collaborate daily with RTL design, physical design, and verification teams
- Mentor and guide junior engineers in DFT methodologies
More Info
Key Skills
About Company
Renesas is an embedded semiconductor solution provider driven by its Purpose To Make Our Lives Easier.As the industrys leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog Connectivity, and Power.
Skills:
boundary scan , ATPG (Automatic Test Pattern Generation), LBIST (Logic Built-In Self-Test), DFT DRC (Design Rule Checking), Jtag, Perl, Python, Tcl, LINT, ASIC design flow, cdc, Scan compression, Scan stitching, Low power DFT Techniques, RTL Coding, ATPG Coverage improvement, DFT STA Constraint development, Analog Phy DFT
Skills:
Dft, MBIST, LBIST, ATPG, Scan Insertion, GLS