Vcs, functional coverage assertions, Questa, Uvm, SVA, systemverilog

SystemVerilog Assertions (SVA), test environments , Gate-Level Simulation (GLS), Test Cases, Low power debug, Constrained-random verification environments, Uvm, systemverilog, Verification test benches, Formal tools, Verification methodologies, Coverage measures, formal verification

Cadence Tools, Gate level simulations, VHDL, Formal verification methodologies, VAMS, Testbench creation, Uvm, systemverilog, Motor control for BLDC BSM motor driver devices

Vcs, Pcie, Python, Tcl, Xcelium, Uvm, systemverilog, APB, Questa, AXI4, AHB, SVA

Regression Analysis, C, Ethernet Protocols, Python, RTL simulation, Uvm, systemverilog, constrained-random verification, testbench architecture, waveform debug, SoC Verification, assertions, functional coverage

Shell, Perl, Python, Tcl, Debugging RTL verification issues, Assertions SVA, UVM methodology, Coverage-driven verification, systemverilog, Functional Verification

Tcl, Python, Perl, systemverilog, Functional Verification, UVM methodology, High-speed networking interfaces, Coverage-driven verification, Ethernet IPs, Emulation platforms or FPGA prototyping

System Verilog, C, Bug Tracking Tool, Git, Models for performance verification, Synopsys, Monitors, Transactors, Performance test plan development, Cadence, RTL simulations

Verilog, advanced stimulus generation techniques, Uvm, coverage-driven verification, systemverilog

Tcl, Python, Perl, Vcs, Uvm, Questa, systemverilog, Verdi