Fpga, Perl, Python, Emulation, RTL, Uvm, systemverilog

Jtag, C, Verilog, System Verilog, Uvm, SOC RTL Design Verification

Computer Architecture, C, Assembly Language, Vcs, Perl, Verilog, Python, System Verilog, Computer Engineering, Raven, UVM methodology, ACK, Microelectronics, Questa, Electrical Engineering

Debugging, Ovm, Verilog, System Verilog, Problem-solving skills, Functional Verification Coverage, Uvm, formal verification, DDR-PHY Design Verification, Design Verification of complex IPs, Low Power Verification, Gate Simulation

Unix, Bug Tracking, Makefile, Shell, Configuration Management, PERL, Python, Verification dashboarding tools, Random stimulus, ARM CPU, PCI Express, Uvm, Functional coverage, systemverilog, AMBA bus protocols, Ethernet bus protocols

C, Uart, Spi, Pcie, I2c, Axi, APB, AHB, simulation and debugging tools from Synopsys, Cadence, Siemens EDA, Uvm, systemverilog

Vcs, functional coverage assertions, Questa, Uvm, SVA, systemverilog

SystemVerilog Assertions (SVA), test environments , Gate-Level Simulation (GLS), Test Cases, Low power debug, Constrained-random verification environments, Uvm, systemverilog, Verification test benches, Formal tools, Verification methodologies, Coverage measures, formal verification

Vcs, Xcelium, JasperGold, formal verification tools, assertion-based verification, Uvm, systemverilog, Questa, VC Formal, SVA, functional coverage