MBIST memory repair, MBIST pattern generation, Xcelium, power-aware DFT, SSN, simulation and debug, ATPG Scan, Tessent-based DFT, Tessent, non-timing simulations, Timing simulations, Advanced DFT, ATPG pattern generation, DRC violation debug fixes, LBIST, memory logic fault models, IJTAG, Retargetting coverage debug

boundary scan , Vcs, Perl, System Verilog, Python, Tcl, primetime, Logic Equivalency checking, Jtag protocols, memory BIST, TetraMax, Gate level simulation debugging, Scan and BIST architectures, ATPG, EDA Tools, Tessent tool sets, TestMax

automation, Scripting, scan compression, BSCAN, MBIST, Siemens Tessent, SSN TestKompress, DFT architecture, ATPG, EDA Tools, Synopsys TetraMAX, DFTMAX, LBIST, IJTAG

boundary scan , Vcs, Perl, Python, System Verilog, Tcl, Memory BIST, primetime, Logic Equivalency checking, TetraMax, Scan and BIST architectures, JTAG protocols, ATPG, EDA Tools, Tessent tool sets, TestMax

Dft, ATPG, MBIST, CCS JTAG

boundary scan standards, test pattern generation, fault isolation methods, scan chain insertion and optimization techniques

boundary scan , Vcs, Perl, Python, System Verilog, Tcl, Memory BIST, primetime, Logic Equivalency checking, TetraMax, Scan and BIST architectures, JTAG protocols, ATPG, EDA Tools, Tessent tool sets, TestMax

Test Automation, DFT Techniques, Scan Insertion, ATPG Tools, Fault Simulation, Design Verification, RTL Coding, Debugging Skills, Timing Analysis, DFT Architecture