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DFT Engineer
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Job Description
Role : DFT Engineer
Exp : 5+ Years
Work Location : Bangalore
Industry : Semiconductor
Description
We are seeking an experienced DFT Engineer to join our team in India. The ideal candidate will have a strong background in design for test methodologies and will be responsible for ensuring the testability of our digital designs.
Responsibilities
- Develop and implement DFT methodologies for various projects.
- Create DFT test plans and strategies for new designs.
- Collaborate with design teams to ensure DFT requirements are met from the initial stages.
- Perform DFT analysis and simulations to validate designs.
- Conduct ATPG (Automatic Test Pattern Generation) and fault simulation.
- Work on scan chain insertion and testability analysis.
- Support chip bring-up and debugging efforts during validation phases.
Skills and Qualifications
- 5-12 years of experience in DFT (Design for Test) engineering.
- Strong knowledge of DFT concepts including scan, BIST (Built-In Self-Test), and JTAG.
- Experience with DFT tools such as Synopsys DFT Compiler, Mentor Graphics, or Cadence tools.
- Proficient in digital design and verification methodologies.
- Solid understanding of VLSI design flow and semiconductor technology.
- Familiarity with RTL design languages such as Verilog or VHDL.
- Ability to work collaboratively in a team environment and communicate effectively.
More Info
Key Skills
DFT Techniques
ATPG Tools
Debugging Skills
DFT Architecture
About Company
Skills:
boundary scan , Test Engineering, Functional Testing, Test Execution, Test Methodologies, Testing, DFT tools and flows, Scan Insertion, hardware and simulation-based test suites, MBIST, test coverage analysis, Digital Design, Timing Concepts, test specifications, testability constraints, quality assurance practices, ATPG, RTL synthesis, EDA Tools, bring-up failure analysis, yield improvement, LBIST
Skills:
Pre-silicon DFT verification, Post-silicon validation, Yield improvement, BSCAN, Hierarchical multi-core test strategies, MBIST, Scripting and automation, Scan compression, GLS, Power-aware DFT, ATPG simulation, ATPG, Debug, DFT timing closure, LBIST, ATE test program development, Coverage closure, IJTAG, Silicon bring-up
Skills:
boundary scan , Jtag, Perl, Shell scripting, Python, Tcl, DFT verification, scan compression, Scan Insertion, MBIST, DFT implementation, ATPG, IJTAG
Skills:
boundary scan standards, test pattern generation, fault isolation methods, scan chain insertion and optimization techniques
Skills:
boundary scan , Vcs, Perl, Python, System Verilog, Tcl, Memory BIST, primetime, Logic Equivalency checking, TetraMax, Scan and BIST architectures, JTAG protocols, ATPG, EDA Tools, Tessent tool sets, TestMax