Shell Scripting, Perl, Python, Tcl, Design Compiler, Verdi, ATPG Pattern Generation, RTL Netlist, primetime, JTAG Boundary Scan, Tessent Scan, Fault Coverage Analysis, Synopsys DFTMAX, Tessent ATPG, Tessent MBIST, Test Collateral, Siemens Tessent Tool Suite, Tessent Diagnosis, Scan Insertion, Scan Compression, MBIST Architecture Implementation

logic bist , Unix, Jtag, Linux, Perl, Tcl, scan diagnostics, Verilog RTL, silicon debug, back-annotated gate level verification, Scan compression and insertion, ATPG, at-speed test, Memory BIST and repair scheme implementation, Fault Simulation, IJTAG

boundary scan , Vcs, Perl, System Verilog, Python, Tcl, primetime, Logic Equivalency checking, Jtag protocols, memory BIST, TetraMax, Gate level simulation debugging, Scan and BIST architectures, ATPG, EDA Tools, Tessent tool sets, TestMax

Test Automation, DFT Techniques, Scan Insertion, ATPG Tools, Fault Simulation, Design Verification, RTL Coding, Debugging Skills, Timing Analysis, DFT Architecture

boundary scan , Vcs, Perl, Python, System Verilog, Tcl, Memory BIST, primetime, Logic Equivalency checking, TetraMax, Scan and BIST architectures, JTAG protocols, ATPG, EDA Tools, Tessent tool sets, TestMax

Perl, Verilog, Python, Tcl, Cadence Tools, Modus DFT, Xcelium Simulation, low-power DFT methodologies, Scan Insertion, MBIST, Genus Synthesis, DFT sign-off, clock-gated designs, DFT architecture, VHDL, ATPG, Fault Simulation

boundary scan , Vcs, Perl, Python, System Verilog, Tcl, Memory BIST, primetime, Logic Equivalency checking, TetraMax, Scan and BIST architectures, JTAG protocols, ATPG, EDA Tools, Tessent tool sets, TestMax