Shell, PERL, Tcl, Assura, Skill, Memory layout design, Cadence Virtuoso

matching , Routing, Parasitics, Memory Array Layout, Sram, LVS, NVM, Physical Verification, Calibre, floorplanning, Layout Optimization, Custom Layout, Memory Layout, Cadence Virtuoso, Placement, ERC, Hierarchical Layout, DRC, FinFET Technology, PPA Optimization, Memory Compiler, Rom

parasitic effects, PEX, Cadence Virtuoso Custom Layout, 5nm FinFET, FinFET layout techniques, matching symmetry, LVS, memory custom layout, design-rule requirements, shielding guard rings, SRAM bitcell memory arrays, layout optimization, ERC, DRC, parasitic optimization, sensitive-net routing, Calibre PVS, advanced-node tapeout

cadence schematic capture , Cadence Tools, Calibre, Hercules, Virtuoso Layout, Layout XL

Memory layout flows, Calibre tools, Technology node knowledge

physical closure, Synopsys, top-level memory integration, decoders, memory compiler IPs, bit-cell arrays, Sram, LVS, collaboration with circuit design, layout experience, sense amplifiers, power performance, yield manufacturability, verification PDK methodology teams, Cadence, optimize layouts for area, IR EM challenges, density verification, FinFET design rules, DFM guidelines, memory periphery, DRAM, DRC, layout and physical verification tools

cadence schematic capture , Verification tools - CALIBRE, Cadence Tools, Memory layout design, AI automation in layout, ElectroMigration, Hercules, SKILL Programming, Physical verification LVS, ERC, DRC, Script Programming, Antenna, Chip Integration, Floor-planning, Hierarchy layout