Verilog, VHDL, simulation debugging, DO-254, traceability validation methodologies, coverage-driven verification, systemverilog

Verilog, System Verilog, Assertion Checker Development, Coverage Closure, Functional Coverage Development, Testcase Planning Development, UVM Testbench Coding, IP SOC Verification, Design Verification Failure Debugging

Perl, Verilog, Python, Cadence Incisive, Xcelium, complex testbenches, Uvm, systemverilog, Synopsys VCS, RTL design concepts, VHDL, formal verification, verification environments, Modelsim

simvision , Tcl Scripting, Vcs, Pcie, Verdi, Xcelium, Uvm, systemverilog, APB, Questa, SVA assertion writing, AXI4, AHB, CDC verification, TLP handling

Perl, Python, Tcl, timing calibration, Uvm, DDR5 LPDDR5 verification, error handling, systemverilog, SVA, functional coverage, power-management

Computer Architecture, Shell, Perl, Debugging, Python, formal verification, DDR protocols, Functional Verification, Uvm, systemverilog, Rtl Design

Emulation, Code coverage and coverage closure, Post-silicon validation, ASIC SoC Design Verification, PCIe protocol verification, SoC IP-level testbench development and integration, PCIe Verification IP, Functional coverage, SystemVerilog UVM, Assertions, formal verification

System Verilog, Tcl Scripting, SMMU, Uvm, assertion-based verification, UPF, formal verification, Axi, power-aware verification, coverage-driven testing, SVA, Synopsys Mentor VIPs, CXL 1.1 2.0 3.0, verification methodologies, performance power optimization, random constraint-based testing, PCIe Gen3 Gen4 Gen5 Gen6, Coresight architecture, CHI protocols

C, Perl, Python, Low power verification methods, FPGA emulator software environments, Emulation platforms, Uvm, systemverilog, Industry standard I/O interfaces, AMBA bus protocols, RTL development environments, Baremetal processor environments, Formal verification methods, UPF based low power verification, Transaction level modeling