Jtag, C, Verilog, System Verilog, Uvm, SOC RTL Design Verification

Debugging, Ovm, Verilog, System Verilog, Problem-solving skills, Functional Verification Coverage, Uvm, formal verification, DDR-PHY Design Verification, Design Verification of complex IPs, Low Power Verification, Gate Simulation

Specman, SV, verification tools for simulation and debug, Uvm

arm architecture , C, Ovm, Jtag, Perl, Verilog, Python, System Verilog, CPU architecture, interconnects, Uvm, power management techniques, debug architecture protocols, coherent fabrics, VHDL, SoC Verification, SVTB

Axi, APB, RISC-V, Uvm, Microarchitecture-level verification, AHB, Processor Architecture

C, Uart, Spi, Pcie, I2c, verification methodologies, assertion-based verification, coverage-driven verification, constrained-random testing, SystemVerilog UVM, Axi, SoC Verification, APB, AHB, simulation and debugging tools from Synopsys

Unix, Bug Tracking, Makefile, Shell, Configuration Management, PERL, Python, Verification dashboarding tools, Random stimulus, ARM CPU, PCI Express, Uvm, Functional coverage, systemverilog, AMBA bus protocols, Ethernet bus protocols