Verilog, Fpga, VHDL, systemverilog, ASIC Design, Synthesis Tools, Timing Analysis, Verification Methodologies, Physical Design, low power design

VLSI FIFO arbitration techniques, static QCs viz LINT CDC RDC CLP VCLP, design and integration for various in-house vendor IPs subsystems and SoC, RTL Coding, QC tools flows and IPXACT, constraints like SDC UPF

Pcie, Verilog, JESD204B, Isp, SERDES, Intel Quartus, systemverilog, Xilinx Vivado, Synthesis, VHDL, FFT, Video Processing Pipelines, MIPI Interfaces, CORDIC Algorithms, FIR Filters

Design Compiler, primetime, Vivado, SDC timing constraints, Genus, Tempus, VLIW, FPGA prototyping, systemverilog

rtl development , static timing analysis, Verilog, Digital Signal Processing, LINT, Synthesis, Debug, LEC, Simulation, Matlab modeling, FPGA prototyping

Matlab Simulink, RTL Verilog, mixed-signal verification, digital PWM modulators, digital design tools, systemverilog

Debugging, Verilog, Computer Architecture, LINT, cdc, RTL simulation, Execution units, Synthesis-aware coding, Caches, RISC-V ISA, CPU microarchitecture, systemverilog, Rtl Design, Memory hierarchy, CPU pipelines, CPU performance optimization, RTL quality checks, Instruction decoding, Microarchitectural trade-offs, ARM processor architecture, formal verification

code coverage , Verilog, System Verilog, LINT, cdc, AXI protocol, Low power synthesis, Formality, SoC level Synthesis, UPF, Rtl Design, Synthesis, AMBA, Timing Analysis, RTL Coding, AHB, ip development, functional coverage, front-end design tools

LINT, SDC constraints, cdc, ASIC SoC development, Timing Analysis, systemverilog, digital design concepts, VHDL, Functional Verification, RTL debugging, Timing Closure, RTL design using Verilog

Coding Methodology, RTL Linting, Synthesis, Design Compiler, primetime, Timing Closure, Genus, SDC Constraints, Tempus, systemverilog