Verilog, Rtl Design, Logic analyzers, systemverilog, DDR memory controller calibration, Calibration algorithms

Embedded C, Uart, I2c, Spi, Timers, Python, Device Drivers, Microcontrollers, DMA

manufacturing processes , product life cycle , Plm, project management, quality value engineering, tolerance stack-up analysis, Creo, production costing, Pdm, product design development, CAD Tools

regulators , references, power-distribution functions, ADCs, noise matching, Filters, mixed-signal design, variability, Spectre, DACs, Feedback, Amplifiers, circuit trade-offs, Analog Design, Cadence Virtuoso, line interfaces, clock-generation circuits, CMOS device behaviour

Python, yield enhancement, Claudecode, Mentor Graphics DRV RVE, Unit Process Development, CAD Tools, Semiconductor device physics, VLSI silicon processing, Test Structure Development, Product Engineering, process integration, Cadence Virtuoso, K2view

Noc, Usb, Vcs, DDR, Shell, Perl, Pcie, Ethernet, Python, Verdi, IUS, UVM environments, SystemVerilog UVM, GLS, coverage closure, debug tools, testbench architecture, Axi, IP SOC verification, Questa, CXL, CPU-based verification

Routing, Physical Verification, Physical Design, EDA Tools, floorplanning, Placement, Timing Closure, DRC, LVS

Verilog, DC analysis, netlist simulation, latch based designs, spice correlation, transient analysis, spice simulators, Gate level simulation, Timing Libraries, Circuit Simulation, MOS switch level models, circuit characterization

Usb, C, C++, Debugging, Test Plan, Object Oriented Programming, Writing Test Cases, Oop, DDR, Ethernet, Pcie, Perl, Tcl, Function coverage, Coverage driven verification, Uvm, IP Subsystem SOC ASIC Verification, Axi, Code coverage analysis, CXL, Test bench development, Simulation, System-Verilog