Clp, Automation, SDC constraints development, Synthesis, Timing Closure, LINT, LEC, AI scripting, Prelayout STA, cdc, Postlayout STA, RTL Netlist based static checks, SDC generation

Clp, Automation, LINT, cdc, Prelayout STA, SDC generation, AI scripting, SDC development, LEC, Low power aspects, RTL Netlist based static checks, Fisthail, Timing Closure, Synthesis, Excellicon, Postlayout STA, Timing Constraints, TCM

Timing ECO generation, Block and SoC level timing convergence, low power design, Block and SoC level equivalence check, Block and SoC level Synthesis, Sta

STA Engineer, constraint development

Sta, GLS, post-layout STA, Synthesis, SDF generation, LINT, LEC, cdc, primetime, Tempus, MMMC analysis, ETM timing model validation, Timing Closure, SDC constraints development, Dft

ETM Timing model generation, MMMC, Synthesis, SDF generation, primetime, Tempus, LINT, cdc, Dft, Sta

DFT modes in STA timing closure, RTL-to-GDSII implementation, Constraint creation and maintenance, PPA optimization, Timing closure fundamentals

Dft

static timing analysis, Python, Tcl, primetime, Tempus, high-speed design timing convergence, constraints synthesis, Clock Tree Synthesis, ECO flows