STA Engineer

monte carlo , Perl, Python, Tcl, FineSim, Hspice, PT Tempus, Spice, Layout Parasitic Extraction, Signal Integrity, ICC, digital flow design, primetime, Innovus, ASIC back-end design flows, STA setup, Timing Analysis

synopsys primetime , Debugging, Python, Perl, Tcl, OCV, timing closure techniques, latency, multicycle paths, derates, MMMC concepts, SDC timing exceptions, timing constraints development, POCV, ECO methodologies, clock uncertainty, Case Analysis, setup hold analysis, Cadence Tempus, clock tree, path-based analysis, jitter, false paths, Timing Closure, AOCV, skew

Timing Concepts, low-power design and multi-voltage domains, STA tools like Synopsys PrimeTime, synthesis and place route flows

PERL, Python, Tcl, Synthesis, Cadence

Sta, RTL2GDS, physical design EDA tools, Cadence, Synopsys, Synopsis Primetime