Position: ASIC STA Engineer (BB60FT RM 4332)
Role : Looking for an experienced ASIC STA Engineer with strong hands-on expertise in pre/post-layout STA and timing closure.
Key Responsibilities
- Perform STA, timing analysis, and timing closure for ASIC designs.
- Develop and debug SDC constraints at block/top level.
- Perform MMMC analysis in Functional & DFT modes.
- Work on Setup/Hold, clock, timing exceptions, and PVT corners.
- Use PrimeTime / Tempus for timing sign-off.
- Support SDF generation, GLS, and ETM/timing model validation.
- Work with RTL, Synthesis, Physical Design, DFT, and SoC teams.
- Support tape-out and timing sign-off activities.
Must Have
- 6+ years of strong STA experience.
- Strong pre-layout & post-layout STA experience.
- Hands-on MMMC & timing closure.
- Strong SDC/constraints development.
- Experience with PrimeTime and/or Tempus.
- Experience with multiple tape-outs.
- Good understanding of Synthesis, DFT, LEC, Lint & CDC.
