Perl Shell Scripting, Scan Insertion, Stuck at Transition ATPG, Production enablement, Synopsys Tetramax DFTMAX, DFT Silicon bring up expertise, Silicon Debug for Phasing closure, Yield Analysis Debug, Test cost reduction analysis, VCS simulation tool, Scan Architecture, GLS Timing and Power Aware Simulations, IDDQ Pattern Generation, Verilog RTL design, ATPG pattern generation, Mentor testkompress, Post Silicon Bring Up Planning, Scan features

Shell, Perl, Python, Tcl, ATPG and advanced fault models, STA and DFT timing closure, DFT design architecture and verification, MBIST, Siemens Tessent, Synopsys TestMax, TetraMax, Cadence Modus, BISR, LBIST, hierarchical DFT and core-wrapper methodologies

Non-volatile Memory (Flash, Dft, MRAM, MBIST, ReRAM, Synopsys, iJTAG IEEE 1687, SoC MCU Architecture, TestMAX, Functional Safety, power management, JTAG IEEE 1149.1, ATPG, Scan Compression, Mentor, Tessent, Audio, Rf, Mixed-signal Design, LBIST, Ate, Digital Design Flows

boundary scan , logic bist , Test Automation, DFT Methodologies, Scan Design, Fault Simulation, ATE Programming, Design Debugging, DFT Architecture, Timing Analysis

Perl Shell Scripting, Scan Insertion, Production enablement, Stuck at Transition ATPG, Synopsys Tetramax DFTMAX, DFT Silicon bring up expertise, Silicon Debug for Phasing closure, Yield Analysis Debug, Test cost reduction analysis, Scan Architecture, VCS simulation tool, GLS Timing and Power Aware Simulations, IDDQ Pattern Generation, Verilog RTL design, ATPG pattern generation, Mentor testkompress, Scan features, Post Silicon Bring Up Planning

Timing Analysis, DFT insertion flows, IEEE1500, Debug and Analysis of failures, equivalency checks, IEEE1687, JTAG 1149.1, SoC ASIC Digital Design, Cadence tools and flows, Verification of ATPG testbenches, scan chain insertion, LBIST, compression scan insertion

Verilog, Scan Insertion, Synopsys, DFT tools, systemverilog, Mentor Siemens Tessent, ATPG, Gate-Level Simulation, Cadence

bist , boundary scan , Soc Architecture, Tcl, Jtag, Python, Perl, MBIST, Scan, EDA Tools, ATPG, Rtl Design, Tessent, Fault Simulation, Cadence Modus, Synthesis, Synopsys DFT Compiler, DFT flows, Timing