DFT Engineer
DFT Engineer
Wenger & Watson Inc.This job is no longer accepting applications
Job Description
Hiring: DFT Architect / Principal DFT Engineer
Locations: Bangalore
Experience: 7+ years
We are looking for experienced DFT Architects / Principal DFT Engineers to drive DFT architecture, methodology, and implementation for next-generation high-performance SoCs and IPs.
Key Responsibilities
- Define end-to-end DFT architecture and test strategy for complex SoCs
- Lead Scan/ATPG, MBIST, LBIST, JTAG, IJTAG and IEEE 1500 implementations
- Drive hierarchical DFT integration, test-mode clocking and power-aware test methodologies
- Optimize test time, test data volume and manufacturing cost
- Collaborate with RTL, Architecture, Physical Design and Product/Test Engineering teams
- Lead DFT verification, post-silicon bring-up, ATE validation and failure analysis
- Evaluate and establish DFT flows using leading EDA tools
Must-Have Skills
- 10–15+ years of hands-on DFT design, architecture and verification
- Strong expertise in ATPG and advanced fault models
- Experience with MBIST/BISR and LBIST
- Expertise in hierarchical DFT and core-wrapper methodologies
- Proficiency with Synopsys TestMax/TetraMAX, Siemens Tessent or Cadence Modus
- Strong understanding of STA and DFT timing closure
- Strong scripting skills in Tcl / Perl / Python / Shell
More Info
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Key Skills
About Company
Skills:
Perl, Logic Design, Python, DFT Engineering, SV, Post Silicon Testing, Coverage metrics, Constrained random testing, Uvm, Profiling Tools, Architecture Verification
Skills:
Jtag, Dft, ATPG, Scan Insertion
Skills:
Perl, Shell scripting, Scan Insertion, Stuck at Transition ATPG, silicon debug, DFT Silicon bring up expertise, Yield Analysis Debug, Test cost reduction analysis, VCS simulation tool, Scan Architecture, GLS Timing and Power Aware Simulations, IDDQ Pattern Generation, Synopsys Tetramax, SOC Tape-Outs, Verilog RTL design, DFTMAX, ATPG pattern generation, Mentor testkompress, Post Silicon Bring Up Planning, Scan features
Skills:
Scripting skills: Tcl, boundary scan , Vcs, System Verilog, Memory BIST, primetime, Logic Equivalency checking, Post-silicon validation and debug, P1687, TetraMax, Gate level simulation debugging, ATE patterns, JTAG protocols, ATPG, EDA Tools, BIST architectures, Tessent tool sets, TestMax
Skills:
MBIST Insertion Verification, ATPG Coverage Analysis Debug, Scan Insertion Compression, Boundary Scan Verification, Mentor Cadence Synopsys Tools