DFT Engineer
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Hiring: DFT Architect / Principal DFT Engineer
Locations: Bangalore
Experience: 7+ years
We are looking for experienced DFT Architects / Principal DFT Engineers to drive DFT architecture, methodology, and implementation for next-generation high-performance SoCs and IPs.
Key Responsibilities
Must-Have Skills
Job ID: 153888789
Skills:
Perl Shell Scripting, Scan Insertion, Stuck at Transition ATPG, Production enablement, Synopsys Tetramax DFTMAX, DFT Silicon bring up expertise, Silicon Debug for Phasing closure, Yield Analysis Debug, Test cost reduction analysis, VCS simulation tool, Scan Architecture, GLS Timing and Power Aware Simulations, IDDQ Pattern Generation, Verilog RTL design, ATPG pattern generation, Mentor testkompress, Post Silicon Bring Up Planning, Scan features
Skills:
Non-volatile Memory (Flash, Dft, MRAM, MBIST, ReRAM, Synopsys, iJTAG IEEE 1687, SoC MCU Architecture, TestMAX, Functional Safety, power management, JTAG IEEE 1149.1, ATPG, Scan Compression, Mentor, Tessent, Audio, Rf, Mixed-signal Design, LBIST, Ate, Digital Design Flows
Skills:
DFT methodologies, PDL development, pattern validation, post-silicon pattern handoff, Siemens Tessent tools, gate-level DFT verification
Skills:
Scan Insertion, ATPG, Silicon bring-up knowledge, Tessent DFT Compiler, MBIST, LBIST
Skills:
Perl Shell Scripting, Scan Insertion, Production enablement, Stuck at Transition ATPG, Synopsys Tetramax DFTMAX, DFT Silicon bring up expertise, Silicon Debug for Phasing closure, Yield Analysis Debug, Test cost reduction analysis, Scan Architecture, VCS simulation tool, GLS Timing and Power Aware Simulations, IDDQ Pattern Generation, Verilog RTL design, ATPG pattern generation, Mentor testkompress, Scan features, Post Silicon Bring Up Planning
