Usb, Vcs, DDR, Pcie, Ethernet, System Verilog, Xcelium, UVM methodology, UCIE, Axi, Questa, CXL

Makefile, Perl scripting, Verilog, Oop Concepts, Ruby, System Verilog, Post-silicon debugging, CPU architecture, Verification flows, Rtl Design, Asic Design Verification, JTAG protocols, Digital Design, Debugging firmware, Assembly language programming

System Verilog, SV UVM based test benches, scripting languages such as Perl, HDLs like Verilog, debugging RTL TB issues using Verdi or similar tools

Pcie, Perl, Python, Tcl, protocol-level debugging, simulation and debug tools, verification methodology, UCIe, Uvm, FDI, systemverilog, coverage closure, CXL, RDI, SVA

Perl, Verilog, Python, Uvm, SVA, systemverilog

C, System Verilog, SoC Verification

Shell, Perl, Verilog, Python, Tcl, LINT, Makefiles, Cadence Xcelium, JasperGold Formal, Cadence VCS, QuestaSim, Uvm, systemverilog, Questa Formal, VHDL, Modelsim

static timing analysis, Digital Logic Design, Perl, Verilog, Python, Scripting, Tcl, Synthesis, cdc, memory subsystems, SOC design, Uvm, IP integration, systemverilog, Rtl Design, Axi, formal verification, EDA tool flows, LINT, Verification, Microarchitecture, bus architectures, automation of design flows

Test Planning, C, Systemc, Shell, Verilog, Tcl, Python, power-aware verification using UPF, systemverilog, NoC bus and interconnect verification, assertions, transaction-level modeling, UVM-based testbench development, constrained-random verification, formal verification