Scripting Language, Python, SV, IJTAG protocol, Functional coverage analysis, Test bench development, Test cases coding, Uvm

Debugging Expertise, SoC Verification, Uvm, Verification Planning, C DPI Development, Scripting and Automation, systemverilog, Hardware-Software Integration, Coverage-Driven Verification

Nvme, Usb, Shell, Tcl, Verilog, System Verilog, Ethernet, Python, Pcie, Perl, DDR, UPF Low Power Verification, System Verilog Assertions, Uvm, Linux development environments, CHI, formal verification, CXL, Axi, NLP Testbench Verification, ASIC design flows

simvision , python, perl, SV-UVM, Verdi, Verisium, Xcellium, Digital Simulation Tools, virtuoso

Version Control Systems, Soc Architecture, Asic Design Verification, BFMs, UVCs, Regression automation, Functional and code coverage methodologies, Uvm, SoC IP verification environments, systemverilog, VIPs

Scripting, Soc Architecture, Shell, Perl, Version Control Systems, System Verilog, Python, Debug, Uvm, SoC IP verification environments, coverage closure, BFMs, UVCs, regression automation, VIPs

System Verilog, Uvm, SVA assertions