Noc, Usb, Vcs, DDR, Shell, Perl, Pcie, Ethernet, Python, Scripting, Verdi, IUS, Uvm, GLS, systemverilog, debug tools, Axi, IP SOC verification, Questa, CXL, CPU-based verification

Nvme, Usb, Shell, Tcl, Verilog, System Verilog, Ethernet, Python, Pcie, Perl, DDR, UPF Low Power Verification, System Verilog Assertions, Uvm, Linux development environments, CHI, formal verification, CXL, Axi, NLP Testbench Verification, ASIC design flows

Shell, Version Control Systems, System Verilog, Python, Scripting, Soc Architecture, Perl, performance features, functional and code coverage methodologies, Advanced SystemVerilog, X86 based SOC DV, Uvm, coverage closure, Security, BFMs, UVCs, power management, regression automation, memory subsystems, Debug, interconnects, SoC IP verification environments, Asic Design Verification, debugging skills, SoC verification methodologies, simulation and verification tools, VIPs

Vcs, System Verilog, Verdi, DVE, Xcelium, Questa, SVA assertions, Uvm

Shell, Version Control Systems, Scripting, System Verilog, Python, Soc Architecture, Perl, performance features, functional and code coverage methodologies, Advanced SystemVerilog, X86 based SOC DV, Uvm, coverage closure, Security, BFMs, UVCs, power management, regression automation, memory subsystems, Debug, interconnects, SoC IP verification environments, Asic Design Verification, debugging skills, SoC verification methodologies, simulation and verification tools, VIPs

Shell, Version Control Systems, Scripting, System Verilog, Python, Soc Architecture, Perl, performance features, functional and code coverage methodologies, Advanced SystemVerilog, X86 based SOC DV, Uvm, coverage closure, Security, BFMs, UVCs, power management, regression automation, memory subsystems, Debug, interconnects, SoC IP verification environments, debugging skills, SoC verification methodologies, simulation and verification tools, VIPs

Shell, Version Control Systems, Scripting, System Verilog, Python, Soc Architecture, Perl, performance features, functional and code coverage methodologies, Advanced SystemVerilog, X86 based SOC DV, Uvm, coverage closure, Security, BFMs, UVCs, power management, regression automation, memory subsystems, Debug, interconnects, SoC IP verification environments, Asic Design Verification, debugging skills, SoC verification methodologies, simulation and verification tools, VIPs

Jtag, System Verilog, Python, Pcie, Perl, UVM methodology, High speed USB, UltraSoC, RISC Debug Architectures, Design for Debug, Tessent Embedded Analytics

rtl verification , SystemVerilog PLI coding, Verilog simulations, Sram, AI-assisted tools, Timing Analysis, DRAM, UVM Test Bench