C, Vcs, Verilog, Perl, spyglass, formal verification, Hardware Emulation Platforms, systemverilog, ASIC Design, cdc, Rtl Design, ASIC SoC development cycle, EVE, Veloce

Digital RTL Design, VHDL, Timing Analysis, Logic Synthesis, Low-Power Design Techniques, systemverilog

bist , C, Vcs, Verilog, Python, Asic verification, Genus Design Compiler, digital timing constraints, XCelium, high-speed SerDes, SOC interconnect fabrics, ASIC tool flows, Scan Insertion, DFT methodologies, Timing Analysis, systemverilog, FPGAs, ASIC synthesis, Axi, AMBA, Timing Constraints, ATPG, APB, Questa, microcontroller platforms, Cadence Virtuoso, AHB

Static timing analysis, Linux, Lsf, Bitbucket, Git, Unix, Splunk, AI ML, Python, Jenkins, EDA Tools, convolutional Networks, make, GenAI, SW development, CI CD process, Implementation, design layout constraints, DesignSync, debug tools, Power-aware flows, UPF, Clocks, Design Verification, cdc, reinforcement learning, Graph Neural Networks, SDC, Dft, RDC

Version Control Systems, Tcl, Verilog, static timing analysis, Perl, Git, Shell, Perforce, Python, Scripting Languages, AHB, LEC, systemverilog, EDA Tools, LINT, Rtl Design, Synthesis, APB, Axi, SoC Architecture Design, SoC Integration, cdc, formal verification, AMBA protocols, Simulation

ASIC development cycle, ASIC design methodologies, develop solutions, cross-functional teams, Rtl Design, architecture, Verification

Design Verification, ASIC Design, Verification Planning, systemverilog, Rtl Design