Lead Design Verification Engineer
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Lead Design Verification Engineer
Location: Bengaluru, India
Experience: 6–12 Years
About the Role
We're looking for a hands-on Lead Design Verification Engineer to drive functional verification of complex SoC/IP designs. You'll develop scalable verification environments, ensure first-pass silicon success, and collaborate closely with design and architecture teams on next-generation semiconductor products.
What You'll Do
What We're Looking For
Join us to build cutting-edge silicon powering the next generation of computing and connectivity.
Job ID: 152331949
Skills:
Vcs, Pcie, Python, Perl, Ethernet, Tcl, Xcelium, Uvm, Testbench Architecture, LPDDR4, Functional Coverage, Verdi, UCIe, systemverilog, Axi, MIPI, Constrained Random Verification, APB, DVE, USB4, USB3, Questa, CXL, DDR5, DDR4, AHB, SVA
Skills:
Tcl Scripting, Doors, DO-254 development process, Electronics Electrical Engineering, Knowledge of Hardware Board and different components like ADC DAC Serial Memory, RTL development using VHDL, Hardware system design knowledge of digital logic, FPGA verification developing Test case Test procedures Test bench debug and simulation using Modelsim Questasim, FPGA Synthesis Place and Route, Developing timing constraints solving CDC issues timing analysis and timing closures for FPGA, Different bus protocols like I2C SPI QSPI UART AXI DDR3 4 PCIe JTAG, FPGA design tools like Libero
Skills:
Test Case Creation, Shell, Perl, Python, Advanced Debugging skills, Uvm, testbench development, coverage-driven verification, Computer Architecture concepts, Formal Verification techniques, Functional Verification, Rtl Design
Skills:
Tcl, System Verilog, Python, Perl, Uvm, FSDB, Verdi
