Vcs, Tcl, Verilog, System Verilog, Python, Perl, Sec, Questa, spyglass, LINT, Xcelium, cdc, Jasper-FPV, Questa CDC, RDC

Ide, Verilog, System Verilog, Pcie, Scripting, ASIC, Synthesis, Uvm, LINT, RTL, cdc, CXL, Genus

Ide, Verilog, System Verilog, Pcie, Scripting, ASIC, Synthesis, Uvm, LINT, RTL, cdc, CXL, Genus

code coverage , closure , Usb, Test Plan Creation, Verilog, Assertions development, formal verification, Functional coverage, UCIe, Power-aware RTL set-up, SV, Gate-level simulations, Emulation, Fault injection, HVL, Constraint randomization, Automotive IP verification, Analog models, DPHY, UVM methodology, Mixed-mode simulations, Digital verification, Verification environment planning, Functional Verification, GLS debug skills, Simulation and debug, SERDES

Usb, Mac, Perl, Pcie, Ethernet, Shell scripting, System Verilog, Python, Tcl, AHB-Lite, Uvm, AMBA, Axi, APB

test equipment , Usb, Spi, Gpio, Pcie, Perl, Verilog, Debugging, Ethernet, I2c, Python, Tcl, HW testing, traffic analysers, DDR SDRAM, Memory architectures, Rtl Design, VHDL, Xilinx technology and tools, test generators, DMA technologies

synopsys primetime , Routing, Perl, Python, Tcl, CTS, PTPX, Cadence Tempus, SDC, Synthesis, Eco, MMMC, Physical Design, STA Timing Closure, Digital Design

Verilog, multi-clock designs, Synthesis, formal verification, ECO fixes, SoC clocking reset architecture, Logic design RTL coding, SoC design and integration, Timing Concepts, asynchronous interfaces, System-Verilog