memory controllers , Uart, Spi, Hdl Languages, Pcie, Verilog, I2c, Unix Systems, Otn, Uvm, Microsemi FPGAs, systemverilog, Ethernet-based protocols, Axi, quartus, VHDL, scripting tools, Vivado, VMM, Libero

FPGA Design, Verilog, FPGA debugging, VHDL, AMD Vivado, logic analyzers, Intel Altera Quartus, Oscilloscopes, Libero SoC

Hdl, VHDL

Vcs, Pcie, Verilog, Debugging, Python, Scripting, Bash, Digital Logic Design, FPGA Design, Ethernet, Tcl, high-speed interfaces, Xcelium, Simulation Tools, FPGA synthesis, LPDDR4, Altera Quartus Prime Pro, LPDDR5, systemverilog, Axi, Timing Closure, Questa, CXL, DDR5, DDR4

VHDL programming, Xilinx, FPGA development, hardware debugging, Intel Altera, Timing Closure, RFSoC, Vivado, Modelsim, LabVIEW FPGA, Rtl Design, Simulation

hardware bring up , Tcl, C, FPGA Design, System Verilog, Python, test benches, Rtl Design, UVM verification flow, Synthesis, Timing Closure, Verification, Debug, Simulation

Fast Fourier Transform, Digital Signal Processing, Verilog, System Verilog, Xilinx FPGA architectures, FPGA development, OFDM, complex algebra, Vivado, Rtl Design, linear algebra, AXI4 Lite, AXI4 Stream, baseband processing

rtl development , nand flash , Tcl, Verilog, FPGA Design, Python, Bash, Pcie, IP Integrator, Vivado Design Suite, VHDL, ChipScope ILA, Embedded Systems, Xilinx FPGAs

Tcl Scripting, Doors, Knowledge of Hardware Board and different components like ADC DAC Serial Memory, DO-254 development process, Electronics Electrical Engineering, Hardware system design knowledge of digital logic, RTL development using VHDL, FPGA verification developing Test case Test procedures Test bench debug and simulation using Modelsim Questasim, FPGA Synthesis Place and Route, Developing timing constraints solving CDC issues timing analysis and timing closures for FPGA, Requirement analysis and validation, Different bus protocols like I2C SPI QSPI UART AXI DDR3 4 PCIe JTAG, FPGA design tools like Libero