Usb, Mac, Perl, Pcie, Ethernet, Shell scripting, System Verilog, Python, Tcl, AHB-Lite, Uvm, AMBA, Axi, APB

Usb, Fpga, Pcie, Perl, Python, high performance industry standard IO interfaces, emulator software environments, coverage driven verification, directed constrained-random tests, Uvm, systemverilog, MIPI, formal verification, test bench infrastructure, FPGA and emulation platforms, AMBA, transaction level modeling, AXI4

Fpga, Logic Design, Verilog, Sta, Synthesis, Power product design, TCL scripts, Scan Insertion, Timing Analysis, design constraints, Uvm, ATPG generation, regression frameworks, formal verification, Timing Constraints, synthesis scripts, ABV, RTL Coding, micro-architecture, Functional Verification, System-Verilog, Digital Verification

Test Planning, C, Systemc, Shell, Verilog, Tcl, Python, power-aware verification using UPF, systemverilog, NoC bus and interconnect verification, assertions, transaction-level modeling, UVM-based testbench development, constrained-random verification, formal verification

Test Planning, Ovm, Debugging, CHI, Uvm, system simulation tools, AHB, UVM-based test benches, SoC design verification, APB, Axi, emulation models, AMBA protocols

Keysight, Exercisers, LeCroy, PIPE Interface verification, Uvm, PCIe Protocol Gen5, systemverilog, Protocol Analyzers

Makefile, Perl scripting, Verilog, Oop Concepts, Ruby, System Verilog, CPU architecture, Verification flows, Rtl Design, Asic Design Verification, JTAG protocols, Digital Design, Debugging firmware, Assembly language programming

Tcl Scripting, Doors, Knowledge of Hardware Board and different components like ADC DAC Serial Memory, DO-254 development process, Electronics Electrical Engineering, Hardware system design knowledge of digital logic, RTL development using VHDL, FPGA verification developing Test case Test procedures Test bench debug and simulation using Modelsim Questasim, FPGA Synthesis Place and Route, Developing timing constraints solving CDC issues timing analysis and timing closures for FPGA, Requirement analysis and validation, Different bus protocols like I2C SPI QSPI UART AXI DDR3 4 PCIe JTAG, FPGA design tools like Libero

DDR, Usb, Pcie, Ethernet, SV, CXL, Uvm