synopsys tools , .lib generation, python, perl, Tcl, STA tools, PD circuit simulation, ICC2

STA Engineer, constraint development

RTL2GDS, physical design EDA tools, Sta

Sta, RTL2GDS, EDA Tools, Timing Analysis, Physical Design

Sta, GLS, post-layout STA, Synthesis, SDF generation, LINT, LEC, cdc, primetime, Tempus, MMMC analysis, ETM timing model validation, Timing Closure, SDC constraints development, Dft

ETM Timing model generation, MMMC, Synthesis, SDF generation, primetime, Tempus, LINT, cdc, Dft, Sta

DFT modes in STA timing closure, RTL-to-GDSII implementation, Constraint creation and maintenance, PPA optimization, Timing closure fundamentals

synopsys primetime , Static Timing Analysis, post-layout STA, timing constraints validation, setup hold analysis, ECO support, timing signoff SI analysis, signoff activities, clock analysis, low-power timing checks, ASIC SoC physical design flow, path-based timing analysis, Timing Closure

Tcl, Python, Perl, RTL to GDSII, LVF POCV variation formats, Constraint Generation, STA Static Timing Analysis, Cadence Tools, Tweaker Prime Time, Automation scripts, Timing ECO Implementation, Timing Closure, Timing Analysis, Digital design Implementation