C, Verilog, Scripting, RTL testbench debug, interconnects, memory hierarchy, Arm-based SoC architecture, Uvm, UPF, systemverilog, coverage closure, coherency

Test Case Creation, Shell, Perl, Python, Advanced Debugging skills, Uvm, testbench development, coverage-driven verification, Computer Architecture concepts, Formal Verification techniques, Functional Verification, Rtl Design

System Verilog, Jtag, Python, Pcie, Perl, UVM methodology, High speed USB, UltraSoC, Design for Debug, RISC Debug Architecture, Tessent Embedded Analytics

Pcie, Ovm, Scripting, System Verilog, Ethernet, Uvm, HBM2, HBM3, Memory protocols, GDDRx, SVA, AHB, LPDDR4, AMBA standards, APB, High speed SerDes, Axi

Debugging, Uvm, Test Planning and Strategy, systemverilog, Mixed-Signal Verification

ARM M-series core operations, DMA interrupt handling, Debugging using disassembly and Tarmac for ARM cores, C code for ARM processors, UVM testbench development, Cache and interconnect, Cadence simulators and SimVision, Cadence and Synopsys VIPs, AHB and APB interface protocols

Verification IP (VIP), Bus Functional Model (BFM), Pcie, systemverilog, Uvm, UCIe, Protocol Verification, UVM Testbench Development, Synopsys VCS, Verdi