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SOC Design Verification Engineer
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Position Summary
About Samsung Semiconductor India Research (SSIR)Role and Responsibilities
Will be involved in SOC verification and responsible for verifying one or more IP(s)/Block(s) from test plan development to GLS sign-off with code/functional coverage closure. He/she will work closely work with cross-domains team (PD, RTL, DFT) for reviews, debug and for technical discussions.
Required Skills:
. 47 years working experience in Sub-system, SOC level verification (including GLS).
. Experience in developing test bench from scratch -- UVM components : BFM, agents, monitor, scoreboard, checkers et al and 3rd party VIP integration.
. Proficient in coding Pre-Silicon functional verifications tests to verify design to meet spec. requirements.
. Creates efficient test plans for RTL validation and Gate level simulations.
. Expertise in System Verilog, UVM, and/or OVM based verification methodologies.
. Experience in OOPs concepts, coverage driven constrained random validation.
. Must have very good knowledge on AMBA standards (AXI, AHB, APB).
. Looking for individual with Hands-on experience in Memory protocols such as - HBM2/HBM3 OR LPDDR45x OR GDDRx is highly desirable.
. Any experience on high-speed protocols like - PCIe, Ethernet, High speed SerDes is a plus
. Working knowledge of scripting, SVA.
. Execution of DV test plan which includes
. Creation/modification of the test bench.
. Implementation of software/programming sequence.
. Creation/integration of checkers and scoreboards from unit level UVM environment.
. Resolution of compile and simulation errors.
. Innovative optimizations to reduce simulation time.
. Complex failure debug: Isolating design related failure by systematically identifying and eliminating issues related to
Test bench/programming sequence in close collaboration with unit verification engineers, logic designers and architects
. Coverage sign-off - Code (block, expression, fsm), toggle and functional coverage
. Continuous regressions (X-prop, Power-aware and performance runs ) and failure closure
Skills and Qualifications
Experience - 4 to 7 years
Qualifications
Disclaimer
Samsung Semiconductor India Research (SSIR), a division of Samsung R&D India - Bangalore Pvt. Ltdis dedicated to employing a diverse workforce and providing Equal Employment Opportunity to all individuals, regardless of their religion, gender, age, marital status, gender identity, status as a protected veteran, genetic information, status as a qualified individual with a disability, or any other characteristic protected by law.
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Job ID: 143894887
Skills:
C, Verilog, Scripting, RTL testbench debug, interconnects, memory hierarchy, Arm-based SoC architecture, Uvm, UPF, systemverilog, coverage closure, coherency
Skills:
System Verilog, Ovm, Debug, Validation Verification, Uvm, verification architecture, Emulation, validation test suites, coverage closure, test plan execution, Silicon Design, constrained random verification methodologies
Skills:
Usb, System Verilog, Jtag, Ethernet, Python, Pcie, Perl, TSN, UVM methodology, SoC architecture verification, scripting in Linux Unix environments, High speed USB, Design for Debug, ARM based SoC verification
Skills:
C, Verilog, Verdi, Xcelium, JasperGold, Uvm, systemverilog
Skills:
ARM M-series core operations, DMA interrupt handling, Debugging using disassembly and Tarmac for ARM cores, C code for ARM processors, UVM testbench development, Cache and interconnect, Cadence simulators and SimVision, Cadence and Synopsys VIPs, AHB and APB interface protocols
