Job Description
ThunderSoft is looking for a Design Verification Engineer with strong expertise in SystemVerilog/UVM and SoC Verification. The ideal candidate should have hands-on experience in Top-Level Design Verification, AMBA protocols, debugging, and UVM testbench development.
Mandatory Skills
- 2–5 years of experience in ASIC/SoC Design Verification.
- Strong hands-on experience in SystemVerilog (SV) and UVM.
- Experience in Top-Level/SoC Verification.
- Good understanding of RTL, Netlist, Gate Level Simulation (GLS), and Power-Aware Verification.
- Experience in developing and maintaining Top DV builds.
- Strong experience in UVM Testbench Development.
- Hands-on experience with AMBA Protocols:
- AXI3
- AXI4
- AHB
- APB
- GPIO
- ACE-Lite
- ACP
- Good understanding of SoC Boot Flow.
- Experience in debugging bus transaction issues, port-level issues, and regression failures.
- Strong debugging skills using Verdi, VCS, Xcelium, or equivalent simulators.
- Scripting knowledge in Python or Perl.
Roles & Responsibilities
- Develop and maintain Top-Level UVM verification environments.
- Build and validate RTL, Netlist, GLS, and Power-Aware simulation environments.
- Collaborate with Block DV, RTL Design, Physical Design (PI/PD), and DFT teams.
- Debug failures from C-based and SystemVerilog-based test cases.
- Analyze and resolve protocol, bus transaction, and port-level issues.
- Execute regressions, analyze coverage, and drive verification closure.
- Raise defects, track fixes, and ensure high-quality top-level builds.
Good to Have
- Experience with SEC UVM.
- Exposure to AI-enabled verification workflows.
- Knowledge of Cadence/Synopsys AI-assisted debugging.
- Experience with Agentic AI.
