Doors, Tcl Scripting, FPGA Synthesis Place and Route, DO-254 development process, RTL development using VHDL, Hardware system design knowledge of digital logic, Different bus protocols like I2C SPI QSPI UART AXI DDR3 4 PCIe JTAG, FPGA verification developing Test case Test procedures Test bench debug and simulation using Modelsim Questasim, Developing timing constraints solving CDC issues timing analysis and timing closures for FPGA, FPGA design tools like Libero, Electronics Electrical Engineering, Knowledge of Hardware Board and different components like ADC DAC Serial Memory

VHDL programming, Xilinx, FPGA development, hardware debugging, Intel Altera, Timing Closure, RFSoC, Vivado, Modelsim, LabVIEW FPGA, Rtl Design, Simulation

hardware bring up , Tcl, C, FPGA Design, System Verilog, Python, test benches, Rtl Design, UVM verification flow, Synthesis, Timing Closure, Verification, Debug, Simulation

microblaze , synplify , nios ii , Pcie, Vcs, Shell, Tcl, Verilog, Ethernet, Python, DDR, Questa, systemverilog, Lattice FPGAs, Vivado, Modelsim, quartus, VHDL, Xilinx, Intel Altera, ARM SoCs, Axi

Fast Fourier Transform, Digital Signal Processing, Verilog, System Verilog, Xilinx FPGA architectures, FPGA development, OFDM, complex algebra, Vivado, Rtl Design, linear algebra, AXI4 Lite, AXI4 Stream, baseband processing

memory controllers , Spi, Uart, Verilog, I2c, Pcie, Hdl Languages, Libero, Unix Systems, Uvm, Otn, systemverilog, Microsemi FPGAs, Ethernet-based protocols, Vivado, quartus, scripting tools, VHDL, VMM, Axi

Intel/ Altera development tool chains, FPGA Design, cdc, Reverse Engineering, test bench for verification, RTL design using VHDL/verilog, Design of IP cores-protocols-HDLC-SPI, STA and other timing considerations

Verilog, Ethernet, Python, Tcl, FPGA design flow using Vivado, VHDL, SpaceWire, FPGA SoC development kits, Electronic test equipment, Libero EDA tools, Camera link