Fpga, C, Perl, Python, AMBA bus protocols, Automation scripts, Emulation platforms, RTL, Uvm, Transaction level modeling, systemverilog

bandwidth management , Machine Learning, Artificial Intelligence, Microprocessor Cores, industry-standard simulators, hierarchical memory subsystems, Specman E, Debug, IP subsystem SoCs, interconnects, regression systems, congestion control, systemverilog, vector processing units, revision control systems, full verification life cycle, packet processing, constrained-random verification environments, AI ML Accelerators, Verification, standard IP components

C, Verilog, Scripting, coverage closure, verification flows, RTL testbench debugging, memory hierarchy, AMBA protocols, Uvm, systemverilog

Shell, Perl, Verilog, Python, Tcl, UVM methodology, Cadence, systemverilog, Functional and code coverage, Simulation and debugging concepts, Verification tools from Synopsys, Siemens EDA

Verilog, System Verilog, Asic verification, Uvm, cpu design, DDR4, Memory

Usb, DDR, Shell, Pcie, Perl, Ethernet, Python, CHI, SystemVerilog UVM, Axi, CXL, SVA

DDR, Ovm, System Verilog, FPGA verification, protocol verification, validation test suites, Uvm, constrained random verification methodologies, FPGA prototyping, FPGA architecture