ASIC Design Verification Engineer - Verilog/UVM

Our client is looking for an ASIC / SoC Design Verification Engineer to join their team. This is a direct and permanent opportunity.

Skills Required :

- 3-10 years of ASIC Design Verification experience with strong Verilog/SystemVerilog and UVM expertise.

- Strong understanding of SoC/system architecture, CPU/microprocessor architecture (x86/ARM/RISC-V), AXI/AHB/CHI/ACE5, memory controllers and high-speed interfaces.

- Experience with DDR4/DDR5, LPDDR4/LPDDR5, USB, PCIe Gen4/5/6, MIPI, I2C/I3C, SPI and UART.

- Hands-on experience with VCS, NCSIM, Verdi, ModelSim or similar simulation/debug tools.

- Experience in functional verification, testbench development, directed/random testing, functional coverage, code coverage, waveform debugging and root-cause analysis.

- Programming/scripting knowledge in C/C++, Python, Perl/Ruby, with UNIX/Linux experience; assembly knowledge is an advantage.

Responsibilities :

- Develop and execute UVM-based verification environments, test plans and directed/random tests for complex ASIC/SoC/IP and CPU designs.

- Verify processors, buses, memory controllers and high-speed interfaces, and perform simulation, waveform analysis and functional debugging.

- Analyze coverage, debug failures, identify root causes and work with RTL Design, Architecture, Firmware, Software and Validation teams to achieve verification closure.

- Improve verification environments and testbenches, develop coverage properties, support pre/post-silicon validation, and mentor junior engineers where required.