UVM (Universal Verification Methodology), SVA (SystemVerilog Assertions), C, C++, Shell, Pcie, Perl, Arm, Python, Tcl, Systemc, MCU, Hardware Emulation Platforms, RISC-V, UCIe, systemverilog, Verification Methodology, AMBA, Axi, Formal Model Equivalence Checking Tools, formal verification, VC Formal

scoreboard , Nvme, Pcie, Verilog, System Verilog, DDR, Assertions, Functional coverage coding, RTL debugging, Code Coverage analysis, Axi, AMBA protocols, Uvm, AHB

C, Systemc, Algorithm Development, Technical Leadership, MATLAB, Verilog, Python, Research Innovation, Cross-Functional Collaboration, System-Level Power Estimation, VHDL, Simulink, system modeling, Methodology Development

Functional coverage, Assertions SVA, SystemVerilog SV, Uvm, Timing Constraints SDC, Verification, Physical Design PD, Rtl Design

Tcl, Version Control, Vcs, Perl, Python, RTL simulation, verification methodologies, Uvm, assertion-based verification, CI CD, systemverilog, Questa, functional coverage

Perl, Python, Tcl, Xcelium simulation, vManager, Real-Number Modeling, Verilog-AMS, JasperGold, Uvm, SVA, systemverilog

pipelining , Ecos, Design DFT, UPF, Low-power design implementation, MCMM synthesis, Physical Synthesis, STA timing closure, Multi-clock domain designs, Netlist delivery, Synthesis methodologies, Timing Constraints, Timing constraints validation, formal verification

Algorithms, Java, data structures, Python, IP-XACT, software engineering principles, Uvm, systemverilog

Pcie, Verification IPs, Regression systems, Simulation environments, VIP abstraction layers, Industry-standard simulators, CXL, Transaction-based verification methodologies, Revision control systems, Uvm, Assertions

Perl, Verilog, Python, Tcl, Uvm, VHDL, systemverilog