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Job ID: 147258335
Skills:
needs assessment , Ms Office, Optioneering, Infoworks ICM, Urban drainage modelling, Model verification, Waste water modelling, Gis Software
Skills:
synopsys tools , Verilog RTL coding, Power Compiler, formal verification tools, IC Compiler, primetime, Design Compiler, CMOS VLSI development, Digital Design
Skills:
rtl verification , Perforce, Pytest, Sonarqube, Gitlab, Python, Git, Tcl, power management, Power Artist, UPF, Structural Low power design, Mixed signal power analysis, EDA Tools, Power Gating, Power-aware Simulation, Voltage regulators, Power Isolation, Power Island, Power analysis and optimisation methods, Prime-Power RTL, Low Power Methodology, Joules, Architectural analysis, ASIC design flows, Object-oriented programming in Python, VSCode
Skills:
arm architecture , C, Usb, Tcl, Ethernet, Perl, Pcie, DDR, Uvm, Synopsys, scoreboards, BFM, TLMs in SystemC, eMMC, Mentor, monitors, Cadence, assertion-based formal verification tools, ARM verification tools, hardware emulation support
Skills:
Unix, Shell, C, Linux, Perl, Verilog, Python, Uvm, systemverilog
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