Synopsys IC Validator, Custom Compiler, 7nm FinFET technology, Cadence Virtuoso Layout Suite, ERC checks, Cadence Pegasus, high-speed analog and mixed-signal layout design, DRC, Calibre DRC LVS PEX, LVS

analog circuits , Circuit Design, Custom Layout, Mentor, LVS, Physical Verification, ERC, DRC, Siemens, Synopsys, Cadence Virtuoso, Layout Design

Synopsys, analog and mixed-signal AMS design, Analog Layout, LVS, Mentor Graphics, Cadence Virtuoso, DRC, post-layout simulation

Custom Analog Layout, Hercules, SKILL Programming, PDK maintenance, semiconductor process technologies, LVS, Physical Verification, Calibre, Assura, custom layout methodologies, Virtuoso XL, ERC, DRC, PCell development, fabrication concepts, Cadence Virtuoso

shielding , Layout verification tools, Analog Custom Layout Design, Advanced process nodes foundry rules, Common centroid, TI Texas Instruments project environment, DRC LVS ERC EM IR checks, Cadence Virtuoso, ESD latch-up prevention, Matching symmetry, Guard rings

matching , Bandgap Oscillators, xACT, LVS, EM, IR drop, Cadence Tools, parasitic effects, MXL, reference circuits, LVS DRC PEX EMIR verification flows, Quantus, GXL, EXL, Xl, Voltus, Calibre DRC, LDOs, StarRC

Dac, Full Custom Analog Layout, Analog Mixed-Signal Layout, RF Layout, Pll, LNA, mixers, VCO, ADC, Cadence Virtuoso XL, Cadence Virtuoso GXL, Calibre, DRC, LVS, ERC, Antenna Checks, Device Matching, Symmetry, Common Centroid, Interdigitation, Physical Verification, Layout Closure, Advanced Process Nodes

rc extraction , bandgap references , shielding , matching , Tcl, Perl, Dfm, high-speed analog custom layout, LVS, latch-up strategies, EDA Tools, clock routing, ADC, Esd, Cadence Virtuoso, ERC, DRC, LDOs, Power Planning, Skill, SERDES, Pll, EMIR analysis

Electron migration, Analog layout design, Voltage drop, Process design rules, Signal planning, Micro-floor planning, High speed SerDes layouts, IR ESD, TSMC N3 technology, Design verification tools