Analog Layout Engineer
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Hiring experienced Analog Layout Engineer - Leading Global semiconductor Design Organization
Experience: 4 to 12 Years
Location: Hyderabad & Bangalore
We are looking for experienced Analog Layout Engineers to work on next-generation Analog, Mixed-Signal, and RF IC designs. This role offers the opportunity to work on advanced semiconductor technologies, lead custom layout activities, and collaborate with global engineering teams to deliver high-performance silicon solutions.
Key Responsibilities:
Hands-on experience in Custom Analog Layout for blocks such as PLL, DLL, LNA, VGA, ADC, DAC, LDO, Bandgap, VCO, and RF Transceivers.
Strong expertise in Cadence Virtuoso/Virtuoso XL, SKILL Programming, and physical verification tools such as Calibre, Assura, and Hercules.
Experience in PCell development, PDK maintenance, and custom layout methodologies.
Strong understanding of physical verification (DRC/LVS/ERC), semiconductor process technologies, and fabrication concepts.
Ability to lead and mentor a team of layout engineers while acting as the technical focal point for customers.
Good understanding of analog design concepts with exposure to digital Place & Route being an added advantage.
Interested candidates can share their resume at: [Confidential Information]
Job ID: 151985633
Skills:
Verification Tools, Cadence Virtuoso Layout Editor, Cadence LVS, Calibre RVE
Skills:
Synopsys IC Validator, Custom Compiler, 7nm FinFET technology, Cadence Virtuoso Layout Suite, ERC checks, Cadence Pegasus, high-speed analog and mixed-signal layout design, DRC, Calibre DRC LVS PEX, LVS
Skills:
analog circuits , Circuit Design, Custom Layout, Mentor, LVS, Physical Verification, ERC, DRC, Siemens, Synopsys, Cadence Virtuoso, Layout Design
Skills:
manufacturing processes , Calibre, Analog Layout, Cadence Virtuoso XL, Design for manufacturability, Signal integrity analysis, Parasitic Extraction
Skills:
Synopsys, analog and mixed-signal AMS design, Analog Layout, LVS, Mentor Graphics, Cadence Virtuoso, DRC, post-layout simulation
