arm architecture , Axi, verification methodologies, APB, Uvm, verification tools for simulation and debug, AHB

Tcl, Verilog, Python, Shell, Git, VHDL, Uvm, Xilinx Vivado, systemverilog, Xcelium

Jtag, Gpu, Soc, Dsp, C Shell, Tcl, System Verilog, Python, Perl, Uvm, Ip, Ai, AHB, APB, Axi, AMBA protocols

chipscope , C, Soc, Pcie, Perl, Verilog, Python, Tcl, Xilinx FPGA, ONFI, Vivado Flow, LPDDR, HAPS

C Programming, Python, PCIe protocol expertise, MCTP OpenBMC stacks, RDMA RoCE, Linux kernel module development, NVMe host or target driver development, Linux auxiliary bus driver model, Out-of-band device management, Security practices in firmware software development, Multi-function PCIe device architectures, GPU host-side driver development, DRAM architecture, CXL Compute Express Link, ARM SoC architecture

Usb, C, Debugging, Object Oriented Programming, Writing Test Cases, DDR, Ethernet, Perl, Pcie, Tcl, Function coverage, Coverage driven verification, IP Subsystem SOC ASIC Verification, Axi, Code coverage analysis, Test bench development, CXL, Simulation, Eth

scoreboarding, memory controller architecture, AXI protocol, assertions SVA, Uvm, DDR protocol JEDEC specifications, functional coverage, GLS, systemverilog

Makefile, Octave, MATLAB, Digital Signal Processing, Scripting Languages, Perl, Python, functional code coverage analysis, UVM-based testbench infrastructure, HW emulation, FPGA prototyping, formal verification, functional cover point development, Power aware simulations, gate level simulations, APB protocol, IP and SoC level verification, assertion development

Uart, python, Debugging, SV, test cases coding, Uvm, Test bench development, IJTAG, APB, Code and Functional coverage analysis, Axi, BUS Protocols