Usb, Pcie, Perl, Shell scripting, Python, Tcl, Cadence, Mentor, IEEE 1149.1 JTAG, IEEE 1500, DFT architecture, Analog Mixed-Signal test structures, ATPG, EDA Tools, IEEE 1687 IJTAG, Siemens, Synopsys

Vcs, Scan Insertion, ATE patterns, JTAG protocols, Tessent, Gate level simulation, ATPG, Post-silicon validation, P1687, TestMax, TetraMax

Perl, Shell scripting, Python, Tcl, Scan Insertion, ATPG, Scan Compression, MBIST, Siemens Tessent

Perl Shell Scripting, Stuck at Transition ATPG, Production enablement, Scan Insertion, Synopsys Tetramax DFTMAX, DFT Silicon bring up expertise, Silicon Debug for Phasing closure, Yield Analysis Debug, Test cost reduction analysis, Scan Architecture, VCS simulation tool, GLS Timing and Power Aware Simulations, IDDQ Pattern Generation, Verilog RTL design, ATPG pattern generation, Mentor testkompress, Post Silicon Bring Up Planning, Scan features

C, Vcs, Jtag, Perl, Verilog, Python, Tcl, Verdi, MBIST, DFT micro-architecture, Synopsys Tetramax, EDA Tools, Scan, Mentor Tessent

coverage analysis, Scan Insertion, SoC level DFT Activities, ATPG, Timing simulations, Pattern generation, Unit delay

Perl, Scripting, Python, Tcl, scan compression, BSCAN, Simulation, MBIST, DFT insertion, ATPG, LBIST, pattern generation, IJTAG

Silicon Validation, DDR, Sta, RTL Synthesis, ASIC SoC design DFT methodologies, P R Verification, SERDES, Mixed Signal IPs, MBIST, Pll, Dft, ATPG, EDA Tools, Scan, manufacturing test flows