DFT Engineer
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Role and Responsibilities: Scan Insertion, ATPG Pattern generation, Coverage Analysis, Unit delay, Timing simulations, SoC level DFT Activities
Skill Requirements: Scan Insertion, ATPG Pattern generation, Coverage Analysis, Unit delay, Timing simulations, SoC level DFT Activities
Experience: 4 to 8 years
Notice Period-Immediate to 15Days
Qualifications: B.Tech/B.E/M.Tech/M.E
Job ID: 152044735
Skills:
Usb, Pcie, Perl, Shell scripting, Python, Tcl, Cadence, Mentor, IEEE 1149.1 JTAG, IEEE 1500, DFT architecture, Analog Mixed-Signal test structures, ATPG, EDA Tools, IEEE 1687 IJTAG, Siemens, Synopsys
Skills:
Shell, Jtag, Python, Tcl, IEEE 1149.x, scan compression, DFT methodologies, MBIST, DFT EDA tools, IEEE 1687, ATPG, LBIST
Skills:
Vcs, Scan Insertion, ATE patterns, JTAG protocols, Tessent, Gate level simulation, ATPG, Post-silicon validation, P1687, TestMax, TetraMax
Skills:
Perl, Shell scripting, Python, Tcl, Scan Insertion, ATPG, Scan Compression, MBIST, Siemens Tessent
Skills:
Perl Shell Scripting, Stuck at Transition ATPG, Production enablement, Scan Insertion, Synopsys Tetramax DFTMAX, DFT Silicon bring up expertise, Silicon Debug for Phasing closure, Yield Analysis Debug, Test cost reduction analysis, Scan Architecture, VCS simulation tool, GLS Timing and Power Aware Simulations, IDDQ Pattern Generation, Verilog RTL design, ATPG pattern generation, Mentor testkompress, Post Silicon Bring Up Planning, Scan features
