DFT Engineer
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Hiring experienced DFT Engineers - Leading Global semiconductor Design Organization
Experience: 4 to 12 Years
Location: Hyderabad & Bangalore
We are looking for an experienced DFT Engineer to work on next-generation ASIC/SoC designs. The role involves Scan, MBIST, ATPG, DFT implementation, and verification, while collaborating with global engineering teams to deliver robust and high-quality semiconductor solutions.
Key Responsibilities:
Interested Candidate can share their resume at [Confidential Information]
Job ID: 151868601
Skills:
Shell, Jtag, Python, Tcl, IEEE 1149.x, scan compression, DFT methodologies, MBIST, DFT EDA tools, IEEE 1687, ATPG, LBIST
Skills:
Vcs, Scan Insertion, ATE patterns, JTAG protocols, Tessent, Gate level simulation, ATPG, Post-silicon validation, P1687, TestMax, TetraMax
Skills:
Usb, Pcie, Perl, Shell scripting, Python, Tcl, Cadence, Mentor, IEEE 1149.1 JTAG, IEEE 1500, DFT architecture, Analog Mixed-Signal test structures, ATPG, EDA Tools, IEEE 1687 IJTAG, Siemens, Synopsys
Skills:
Perl, Shell scripting, Python, Tcl, Scan Insertion, ATPG, Scan Compression, MBIST, Siemens Tessent
Skills:
Perl Shell Scripting, Stuck at Transition ATPG, Production enablement, Scan Insertion, Synopsys Tetramax DFTMAX, DFT Silicon bring up expertise, Silicon Debug for Phasing closure, Yield Analysis Debug, Test cost reduction analysis, Scan Architecture, VCS simulation tool, GLS Timing and Power Aware Simulations, IDDQ Pattern Generation, Verilog RTL design, ATPG pattern generation, Mentor testkompress, Post Silicon Bring Up Planning, Scan features
