boundary scan , Tcl, Python, Perl, Scripting Languages, test pattern generation, silicon bring-up, scan compression, JTAG IEEE 1149.1, ATPG, DFT EDA tools, post-silicon debug, DFT methodologies, Cadence Modus Genus, memory BIST, Scan Insertion

Tcl, Python, Perl, Scan Architecture, Gate-level Simulation, MBIST, Scan Insertion, ATPG, Scan Compression, DFT Validation, IEEE 1500 standards

Scan insertion and compression, DFT architecture planning, Boundary scan IEEE 1149.1 1149.6 IJTAG 1687, MBIST, Fault grading, ATPG pattern generation, Logic BIST insertion and validation, Synthesis flows, Rtl Design, Sta