congestion management , Perl, Python, Tcl, physical implementation, SoC-level floorplanning, primetime, clock tree architecture, clock gating, Cadence Innovus, power-aware physical implementation, skew management, clock domain partitioning, clocking methodologies, Timing Closure, low-power design techniques, Synopsys ICC2

Tcl, Shell scripting, Python, Fc, Innovous, Tempus, primetime

Static Timing, Routing, Physical Verification, Synthesis, Power Efficiency, Custom Clocking, Physical Design, Placement, floorplanning, Formal Equivalency, IR-Drop

Physical Design Planning, Placement, Floor Planning

synopsys primetime , Routing, Perl, Python, Tcl, CTS, PTPX, Cadence Tempus, SDC, Synthesis, Eco, MMMC, Physical Design, STA Timing Closure, Digital Design

clocking , power integrity , LV EM IR Analysis, ESD Analysis, Physical Design Integration, RTL2GDS Implementation, Signal Integrity, PPA Power DRC Signoff, LVS clean-up, DRC, PNR Floor Plan, Power Mesh, Timing Signoff