Uncore subsystems, Physical Design, FinFET nodes, EDA suites, Cadence, Synopsys, RTL-to-GDSII

Perl, Python, Tcl, Timing Closure STA, RTL-to-GDSII Execution, Red Hawk, Programming Scripting, Fusion Compiler, LEC, Tempus, Cross-Functional Collaboration, Physical Formal Verification, Innovus, Calibre, primetime, PPA Optimization, EDA Tools, VCLP

Scripting, EMIR Signoff flow, Data Analysis, In-rush current profiles, EDA Tools, Dynamic vectored and vectorless Static IR, Power Distribution Network Design, On-die power gating, Problem Solving

Perl, Python, Tcl, primetime, Cadence Innovus, EM analysis, Physical Verification, Signal Integrity, StarRC, Timing Closure, low-power design techniques, Synopsys ICC2

Routing, Sta, CTS, PNR, Physical Design, floorplanning, Timing Closure, Placement, Sign-off

Perl, Python, Tcl, Sta, CTS, pegasus, floorplanning, Cadence Toolchain, Power Grid, Tempus STA, Innovus, Calibre, MMMC, Timing Closure, Sign-off, ECO generation, SI crosstalk analysis, GDSII

Low Power SoCs, Physical Verification, Physical Design, Timing Closure, Floor Planning, Dynamic IR Drop, Package Co-design, Place And Route, Clock Tree Synthesis, IO Planning, Power Grid Design

Rtl Design, Synthesis, RISC CPU IP, Emulation, silicon bring-up, Microarchitecture, Verification, Timing Analysis, Physical Design, SoC design methodology