Static Timing Analysis, primetime, Physical Design, Clock Distribution Circuit Design, Circuit-Level Timing Noise Integrity, Tempus, Interconnect Physical Design, Synopsys Fusion Compiler, Cadence Innovus, Architectural Circuit Co-Optimization

Perl, Python, Tcl, OCV, primetime, Fusion Compiler, ICC2, SI Crosstalk, ECO flows, MMMC, Timing Closure, POCV, AOCV, Clock Tree Synthesis

Static Timing, Routing, Physical Verification, Synthesis, Power Efficiency, Custom Clocking, Physical Design, floorplanning, Placement, Formal Equivalency, IR-Drop

redhawk , Python Scripting, Shell, Perl, Verilog, Tcl, full-chip aspects, Fusion compiler, Formal equivalence, PTPX, ICC2, signoff, IP integration, Timing Verification, Physical Design, primetime, timing convergence, VHDL, PNR, Low Power Checks, EDA Tools

Scripting, EMIR Signoff flow, Data Analysis, In-rush current profiles, EDA Tools, Dynamic vectored and vectorless Static IR, Power Distribution Network Design, On-die power gating, Problem Solving

micro architecture , sign-off convergence, low-power physical design, RTL, electrical checks, ASIC design implementation, Physical Verification, CPU implementation

power integrity , Routing, Perl, Python, Tcl, Chip finishing, Metal fill, Clock Trees, Tapeout checks, Physical Verification, Sealring, Signal Integrity, RTL2GDS flow, Floorplans, Power Distribution Network, Physical Design, Timing Closure, Placement, Physical Sign off, Equivalence Check, Synthesis Constraints

Scripting, Python, Routing, Tcl, CTS, primetime, 3D IC, ICC2, Cadence, LVS, IR Drop, Calibre, Innovus, Physical Verification, HBM, Placement, Si, Chiplets, floorplanning, EM, Full-Chip Physical Design, Advanced Packaging, Timing Closure, DRC, Advanced nodes 7nm or below, 2.5D, EDA Tools, Synopsys

redhawk , Tcl, Perl, Deep sub-micron designs, Dc, Synthesis, Timing Closure, Pt, LVS, ICC, VSLP, Logic equivalence checking, Low Power checking, Calibre, STA timing, Formality, Place And Route, DRC, Physical Design, SOC design