Relevant Experience 12-16 Years – L4
Role: Sr Lead Physical Design
This position is for senior level engineer Full chip level Power Distribution Network Design. He Shall be leading instrumental in power grid planning on SoC level for peak current requirements & to have Dynamic & Static IR drop assessment & closure.
Key Responsiblities
- Ability to Develop & run EMIR Signoff flow at SOC
- Ability to Close EMIR based on Dynamic (vectored and vectorless) & Static IR
- Can provide Feedback on Grid Robustness to SOC floorplan team
- Working with the system, PMIC and silicon package team to model the voltage response of the power delivery network.
- Model of the power delivery networks, including on-die power gating and in-rush current profiles.
- Model of the current profiles and peak current demands of various IPs.
- Strong Skills in problem solving, scripting, data analysis and experience with EDA tools.
- Teamwork / flexibility / ability to thrive in a dynamic environment are very important
Academic Credentials
Bachelors or Master's degree in Computer/Electronics/Electrical Engineering
lectronics/Electrical Engineering
