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Senior RTL Design Engineer

Inotec AMD
Hyderabad, India

Skills:

Perl, Verilog, Shell scripting, LINT, cdc, Connectivity, RTL quality checks, SOC design, VCLP

Early Applicant

Senior RTL Design Engineer

AMD Telecom
Hyderabad, India

Skills:

Perl, Verilog, Shell scripting, LINT, cdc, RTL quality checks, Connectivity, SOC design, VCLP

Early Applicant

Senior RTL Design Engineer

AMD Maquinaria
Hyderabad, India

Skills:

Perl, Verilog, Shell scripting, LINT, cdc, RTL quality checks, Connectivity, SOC design, VCLP

Early Applicant

Senior RTL Design Engineer

Xilinx
X
Hyderabad, India

Skills:

Verilog, Shell Scripting, Perl, Connectivity, LINT, VCLP, cdc, Micro Architecture Definition, SOC design, RTL Quality Checks

Early Applicant

Senior Staff Engineer - RTL Design (ASIC)

Randstad India
Hyderabad, India

Skills:

static timing analysis, Verilog, Debugging, Integration, Synthesis, multi-clock domain architectures, digital design fundamentals, power optimization techniques, low-power design methodologies, micro-architecture development, Physical Design, systemverilog, Dft, Axi, APB, Timing Closure, RTL Coding, Verification, AHB

Early Applicant

Senior ASIC RTL Design Engineer

MosChip Semiconductor
Hyderabad, India

Skills:

Verilog, Asynchronous interface, Synthesis, ECO fixes, SoC clocking reset architecture, Logic design RTL coding, SoC design and integration, Multi Clock designs, System-Verilog, formal verification

Early Applicant
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