Job Title: Senior Staff Engineer - RTL Design (ASIC)
Location: Hyderabad (Hybrid)
Experience: 10+ Years
Client: Confidential (Renowned Product-Based Semiconductor Organization)
Employment Type: Direct Payroll Opportunity
Job Summary
We are seeking a highly experienced Senior Staff RTL Design Engineer to join a leading semiconductor product company. The role involves designing and implementing complex ASIC/SoC solutions while collaborating closely with architecture, verification, DFT, and physical design teams to deliver high-performance, power-efficient products.
Key Responsibilities
- Design and implement RTL for complex IPs and SoC subsystems using Verilog/SystemVerilog.
- Develop micro-architecture specifications and translate them into high-quality RTL implementations.
- Optimize RTL for performance, power, and area (PPA) targets while ensuring scalability and design robustness.
- Collaborate with architecture, verification, firmware, DFT, and physical design teams throughout the development cycle.
- Support synthesis, static timing analysis, timing closure, and physically aware design methodologies.
- Work closely with verification teams to achieve functional correctness and coverage goals.
- Analyze and resolve design issues during integration, implementation, and silicon bring-up phases.
- Contribute to design methodology improvements, automation initiatives, and best practices.
- Mentor junior engineers and provide technical leadership across project teams.
- Support post-silicon validation and debug activities as required.
Qualifications
- B.Tech/M.Tech in Electronics, Electrical Engineering, Computer Engineering, or a related discipline.
- 10+ years of experience in RTL design and development for ASIC/SoC products.
- Strong expertise in Verilog/SystemVerilog and digital design fundamentals.
- Hands-on experience with micro-architecture development, RTL coding, integration, and debugging.
- Strong understanding of ASIC design flow, including synthesis, STA, timing closure, and power optimization techniques.
- Experience with low-power design methodologies and multi-clock domain architectures.
- Familiarity with industry-standard bus and interconnect protocols such as AXI, AHB, APB, or similar.
- Experience working with DFT, verification, and physical design teams in a full-chip development environment.
- Strong problem-solving, communication, and collaboration skills.
- Prior experience in product-based semiconductor companies is highly preferred.
