Search by job, company or skills

X

Senior RTL Design Engineer

Save
new job description bg glownew job description bg glow
  • Posted 5 days ago
  • Be among the first 10 applicants
Early Applicant

Job Description



WHAT YOU DO AT AMD CHANGES EVERYTHING

At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.Together, we advance your career.




SMTS SILICON DESIGN ENGINEER

THE ROLE:

As a member of the Server SoC Group, you will help bring to life cutting-edge designs. As a member of the front-end design/integration team, you will work closely with the architecture, IP design, Physical Design teams, and DFT Design teams to achieve first pass silicon success.

THE PERSON:

A successful candidate will work with Architects, IP Design Teams, own micro architecture definition for one of the chiplet in Server SoC. The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills.

KEY RESPONSIBLITIES:

  • Work with SoC Architects, IP Design Teams and define micro architecture that includes clocking, reset, IO, Fuse Implement SoC Design features/blocks, own connectivity across IP's
  • Work with Physical Design Team and deliver/triage all collaterals required for PD and implement SoC topology networks based on Full Chip floorplan and other Physical Design requirements
  • Own and drive RTL Quality checks/Audit that includes Lint/CDC/VCLP/Connectivity


P
REFERRED EXPERIENCE:

  • Understanding SoC Design aspects that includes Clocking, IO, Latency, Reset, Fuse map, SoC Topology Networks
  • 12+ years of experience in SoC Integration activities and definition of micro architecture
  • Experience with Verilog, Perl/Shell scripting, and all RTL quality checks Triaging and debugging issues reported by Verification teams

ACADEMIC CREDENTIALS:

  • Bachelors or Masters degree in computer engineering/Electrical Engineering
#LI-AA1




Benefits offered are described: .

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD's Responsible AI Policy is available

This posting is for an existing vacancy.

About Company

Xilinx, Inc. was an American technology and semiconductor company that primarily supplied programmable logic devices. The company was known for inventing the first commercially viable field-programmable gate array and creating the first fabless manufacturing model.

Job ID: 148409623

Similar Jobs

Hyderabad, India

Skills:

ShellTclPerlDMAdigital design fundamentalscontrol data path logicprotocol bridgeslow-power design flowssystemverilogpower performance and area optimization techniqueslint CDC RDC synthesis STA constraintsRTL design using Verilogmemory-mapped peripheralsmicro-architecture definitionDftbus fabricsdebugging skills for simulation synthesis and integration issues