Sr. Lead Physical Design - STA

Relevant Experience 11-15 Years

Role : Sr Lead Physical Design Timing Engineer

This position is for Senior Level STA Engineer who will oversee full chip and/or subsystem level STA convergence from early stages to signoff. Taking part in top level floorplan and clock planning. Work closely with logic design and DFT engineers to define and implement constraints for the various work modes including their optimization of runtime

.

Key Responsibilitie

• s Strong experience in ASIC timing constraints generation, validation and timing closur
• e.Expertise in Primetime and timing eco (physical aware) using PT-DMSA - full chip and block lev
• elExperience in IO Timing/ interface budgeting / process margins / corner definitio
• nsFamiliarity with D
• FTProficient in scripting language (TCL/python
• ).excellent timing and flow debugging skil
• lsExperience in ECO generation flow for RTL, pre-physical and post route implementation considering timing, congestion and logic equivalenc
• e.Automation to improve PPA (power/performance/area) and ensure a high-quality design environment for SO
• C.Proficient in scripting language (TCL/python
• ).Hands on experience in reference flows, excellent debugging skill

s.